Embodiments of the invention generally relate to semiconductor manufacturing processes and devices.
As smaller transistors are manufactured, ultra shallow source/drain junctions for sub-100 nm CMOS (complementary metal-oxide semiconductor) devices, such as silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices, are becoming more challenging to produce. Such MOS(FET) transistors may include p-channel MOS (PMOS) transistors, and n-channel MOS (NMOS) transistors, depending on the dopant conductivity types, whereas the PMOS has a p-type channel, i.e., holes are responsible for conduction in the channel and the NMOS has an n-type channel, i.e., the electrons are responsible for conduction in the channel.
Silicon based materials may be used in device creation for MOSFET devices. For example, in a PMOS application, the film in a recessed area of the transistor may be manufactured from silicon-germanium, and for a NMOS application, the film in the recessed area may be SiC. Silicon-germanium is advantageously used to implant more boron than silicon alone to reduce junction resistivity, which improves device performance, and the silicon-germanium interface with the silicide layer at the substrate surface has a lower Schottky barrier than the silicon interface with silicon-germanium, which also decreases series resistance in the device and improves performance. Alternatively, as is known in the art, the device could be made from essentially pure silicon that contains dopants necessary to make the device a P-type or N-type device and may contain implanted Ge.
The recessed areas comprise source/drain extension or source/drain features, which are manufactured by etching silicon to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown silicon-germanium epilayer. The mismatch of lattices between silicon and the silicon-germanium material generates compressive strain which is transferred in the lateral dimension of the junction to create longitudinal compressive strain in the PMOS channel and to increase mobility of the holes and improve device performance. In NMOS applications, increased longitudinal and transverse tensile strain increases the electron mobility in the device. Thus, in either case, the straining of the silicon material is a technique to increase the charge carriers' mobility, which enhances device performance.
Known methods of obtaining strain in transistor devices include two general approaches. A first approach is developing strain at the substrate level before any transistor device is fabricated. This first approach will be referred to herein as the “global” approach, and includes the provision of biaxial strain along two axes. A second approach to obtaining strain will be referred to herein as the “local” approach, and includes adjusting the properties of local films or layers on the transistor device during transistor fabrication to impart uniaxial strain, or stress predominantly along one axis, although this approach could also cause strain along a second axis, namely, the vertical axis. Local strain includes imparting stress to selected transistor regions.
There are various known ways of changing local strain in transistors, and these ways will be referred to herein as “parameters that effect strain” or “stressors.” Sources of local strain include but are not limited to the embedded silicon-germanium in the source/drain regions of a transistor, the etch stop nitride layers of the transistor with built-in intrinsic stress, the strain from the shallow trench isolation (STI), the strain in the polysilicon/metal gate electrode or the sidewall spacer dielectric with in-built intrinsic stress. By modulating or changing a parameter of one of these sources of strain, the strain in the transistor device can be modulated. For example, the dimensions of the spacer, the etch stop, elevation of the source/drain region, the composition of the source/drain region or composition of the etch stop are examples of parameters that can be changed to modulate the strain in a transistor. Current methods of modulating the strain in transistor devices involve changing a single source of parameter for each transistor. For continued device scaling, there is a need to provide increased strain in the channel for sustained device improvements from one technology node to another. Therefore, there is a need to provide methods of increasing the strain in a single transistor device.